(1) Field of the Invention
The invention relates to a method of forming polysilicon resistors in the fabrication of integrated circuits, and more particularly, to a method of forming polysilicon resistors with precisely controlled resistance in the manufacture of integrated circuits.
(2) Description of the Prior Art
Polysilicon resistors have been used extensively in Very Large Scale Integrated circuits (VLSI), such as analog to digital converters and poly-load static random access memories (SRAM). An unfortunate characteristic of polysilicon resistors is their ability to absorb hydrogen to which the resistors are exposed during semiconductor processing. This results in resistance reduction and fluctuation of the resistors. Hydrogen penetration, as well as etch and chemical mechanical polishing (CMP) impact of backend processes, make it difficult to control resistance values precisely.
It has been shown that a metal shield over a polysilicon resistor will reduce the resistance variation of the resistor by avoiding hydrogen penetration. However, the extension of the metal to polysilicon affects the performance of the poly-resistor. The chip size can be enlarged to meet the tight control requirements of the poly resistor, but this is undesirable for cost-efficiency reasons. Double resistor load implantation (P+BF.sub.2) has been proposed to decrease the temperature coefficient of the poly load thereby improving the cell stability of the poly-load SRAM. However, the sensitivity of the poly resistance to implant dosage is too high for manufacturing.
A silicon nitride capping layer has been used to prevent hydrogen diffusion into the polysilicon resistor. For example, U.S. Pat. No. 5,461,000 to Liang and U.S. Pat. No. 5,108,945 to Matthews teach a silicon nitride layer in the range of 500 to 2500 Angstroms over the resistor. Co-pending U.S. Patent Application serial number 09/234.096 to Y. L. Hsu et al filed on Jan. 19, 1999 teaches a silicon nitride layer of 300 to 1000 Angstroms deposited by low pressure chemical vapor deposition (LPCVD). However, such a thick silicon nitride layer is incompatible with the self-aligned contact (SAC) process, which is widely used in SRAM and dynamic random access memory (DRAM) processes to reduce cell size, because the thicker (&gt;100 Angstroms) nitride film acts as an etch stop in the highly selective SAC etch.
U.S. Pat. No. 5,500,553 to Ikegami teaches forming a metal cap over polysilicon resistors to equalize the change in resistance caused by hydrogen atoms diffusing into the polysilicon. U.S. Pat. No. 5,834,815 to Cheng et al also discloses a metal cap over the poly resistor. U.S. Pat. No. 5,384,278 to Singlevich and U.S. Pat. No. 4,604,789 to Bourassa disclose oxide capping layers over polysilicon. U.S. Pat. No. 4,592,128 to Bourassa employs nitride as an implant mask. U.S. Pat. No. 5,728,615 to Cheng et al teaches a thermal treatment in N.sub.2 with a H.sub.2 ambient to equalize the hydrogen concentration in a polysilicon resistor. No capping layer is used, but hydrogen is allowed to penetrate the resistor. U.S. Pat. No. 4,641,173 to Malhi et al show silicon nitride tunneling layers surrounding a vertical poly resistor. The resistance of a vertical resistor is not easy to control because load implantation cannot be used. In addition, while a silicon nitride cap is used to protect the poly resistor from the interpoly oxide, hydrogen atoms can still diffuse into the resistor.